1. Field of the Invention
This invention is concerned with electroplating of semiconductor wafers, and in particular with the formation of copper integrated circuits (IC's) on semiconductor chips.
2. Related Prior Art
The electronics industry is in the process of transitioning from aluminum to copper as the basic metallization for semiconductor IC's. The higher electrical conductivity of copper reduces resistive losses and enables the faster switching needed for future generations of advanced devices. Copper also has a higher resistance to electromigration than aluminum.
The leading technology for fabricating copper circuitry on semiconductor chips is the “Damascene” process (see, e.g., P. C. Andricacos, Electrochem. Soc. Interface, Spring 1999, p. 32; U.S. Pat. No. 4,789,648 to Chow et al.; and U.S. Pat. No. 5,209,817 to Ahmad et al.). In this process, vias are etched through and trenches are etched in the chip's dielectric material, which is typically silicon dioxide, although materials with lower dielectric constants are desirable. A barrier layer, e.g., titanium nitride (TiN) or tantalum nitride (TaN), is first deposited into the trenches and vias by reactive sputtering to prevent Cu migration into the dielectric material and degradation of the device performance. Next, a thin copper seed layer is deposited by sputtering to provide the enhanced conductivity and good nucleation needed for copper electrodeposition. Copper is then electrodeposited into the trenches and vias. Excess copper deposited over the trenches and vias and in other areas (called the “overburden”) is removed by chemical mechanical polishing (CMP). The “dual Damascene” process involves deposition in both trenches and vias at the same time. As used in this document, the general term “Damascene” also encompasses the dual Damascene process.
Damascene electroplating is generally performed on full silicon wafers, which are disks typically 8 inches (200 mm) in diameter and 0.03 inches (0.75 mm) thick. The industry trend is toward wafers of even larger diameters. Currently available wafer plating equipment employs a cathode assembly that includes a metallic backing plate, an insulating plastic housing, and a special metallic ring that makes electrical contact to the copper seed layer around the perimeter of the “plated” side of the wafer, i.e., the side of the wafer that is electroplated with copper. A concentric gasket (or o-ring) of smaller diameter is used to form a seal between the wafer plated-side surface and the plastic housing so as to prevent intrusion of the plating solution into the contact area and to the non-plated side of the wafer (opposite to the plated side). During plating, the electrolyte is pumped through at least one tubular nozzle directed at the wafer surface to provide bath agitation. The wafer is typically plated in the plated-side-down configuration and the cathode assembly is rotated to enhance the rate and uniformity of solution flow across the wafer surface.
Currently available wafer plating systems are cumbersome to automate and do not provide the highly uniform copper deposition across the wafer surface needed to provide the highest quality copper in trenches and vias and to minimize CMP processing time. A key problem is that the gasket or o-ring used to form a seal to the wafer requires a reasonably thick mechanical support structure which protrudes past the wafer plated surface, impeding solution flow and causing nonuniform copper deposition. To accommodate the electrical contact assembly and protective plastic housing, the plating tank is made substantially larger in diameter than the wafer plated area so that the wafer perimeter tends to be overplated because of the additional current path through the additional plating solution. Complicated baffles and shields are used in conjunction with cathode rotation to improve copper plating uniformity but these increase the complexity and expense of automation and do not provide optimum plating results. In addition, the requirement of cathode rotation is more easily fulfilled by exposing the wafer to the solution in the plated-side-down configuration for which trapping of bubbles within fine trenches and vias is a problem.
There is a critical need for an improved wafer plating system that operates in the plated-side-up configuration, provides adequate solution flow over the wafer surface, and prevents overplating of the wafer perimeter. Such an assembly would be valuable in providing more uniform Damascene copper plating and reducing costs for both the wafer plating operation and the subsequent CMP process.
Such an improved wafer plating system could also provide similar advantages for other wafer plating processes. For example, solder bumps for flip chip attachment are often fabricated by electroplating tin-lead solder on wafer pads exposed through a photoresist mask. The pads are electrically interconnected by a metallic seed layer (often gold but other metals are used), which is subsequently removed from non-pad areas of the wafer by wet chemical etching. Typically, the whole wafer is immersed in the plating tank and electrical contact to the seed layer on the wafer plated side is established via spring-loaded, plastic-shielded wires at a few points (usually three). Overplating of pads near the wafer edge is suppressed by use of plastic shielding in the plating solution. It is important that approximately the same amount of solder be plated on all pads within a given IC chip so that the solder balls are sufficiently uniform in height to be coplanar with the flip chip attachment pads on the substrate. As the trend toward IC chip miniaturization continues and solder balls decrease in volume, the requirement for solder plating uniformity across the wafer is becoming more stringent. Even if the coplanarity requirement within individual chips is met, too much solder in the balls can cause bridging that shorts the device. On the other hand, too little solder can result in structurally unsound solder joints because of inadequate underfill in the narrow space available, diminished distance over which stresses caused by thermal expansion mismatches can be relieved, and/or solder joint embrittlement induced by excessive volume fraction of gold contamination from seed or barrier layers. Consequently, there is an increasing need for a wafer plating system enabling pads on wafers to be plated with equivalent amounts of solder.